BI-MOS semiconductor memory having high soft error immunity

摘要

A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by alpha rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage VD and the word line voltage VW satisfy the relation VW<VD+VTH in a read cycle and the relation VW>VD+VTH in a write cycle (where VTH is the threshold voltage of NMOS inside the memory cell).