发明名称 FFT ARITHMETIC UNIT
摘要 <p>PURPOSE:To shorten an FFT (Fast Fourier Transform) operation time by successively storing an A/D-converted data in a storing part and reading at a high speed and using them from latest data retroactively to the past with the timing of FFT operation. CONSTITUTION:An input signal lambda, after it passes through an LPF 1 and a sample holder 2, is digitized by an A/D converter 30. The value is written to the address of a storing part 6 instructed by an address preparing part 7 composed of an up-counter. At the time of starting the FFT, the counted value of the address preparing part 7 is shifted to an address preparing part 9 composed of a down-counter by the signal from a timing controller 10. Next, the address preparing part 9 is decremented at a high speed, the contents of the storing part 6 of the corresponding address are read to an FFT converting part 8 and the FFT conversion is executed.</p>
申请公布号 JPH01228060(A) 申请公布日期 1989.09.12
申请号 JP19880054276 申请日期 1988.03.08
申请人 YOKOGAWA ELECTRIC CORP 发明人 SHIYOUBAYASHI NOBORU
分类号 G01R23/16;G06F17/14 主分类号 G01R23/16
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