| 摘要 |
<p>PURPOSE:To shorten time required for measurement/misrecognition of a binary image by constituting the title circuit so that the access of a processor can be executed even on the way of a processing by using an FIFO memory. CONSTITUTION:In an X.FIFO memory 24, an X<->.FIFO memory 25 and a Y.FIFO memory 26, (x) coordinate data of the leading end of the rise of a binary image signal PD, X coordinate data of the trailing end of the fall of the binary image signal PD and Y coordinate of the leading end of the rise of the binary image signal PD are stored, respectively. In such a way, the foregoing is repeated until one screen is ended. As for these coordinate data stored in respective memories 24-26, as soon as the data are written in each FIFO memory in accordance with a processing procedure stored in a memory 28 through a control bus 20 under the control of a processor 27, they are read out through a data bus 19, and stored in the memory 28. In such a way, to the data stored in respective memories 24-26, a prescribed operation processing is performed by the processor 27 and an image is reproduced, and a necessary processing is executed and said data are outputted to an output terminal 22 through an I/O terminal 29.</p> |
