| 摘要 |
PURPOSE:To eliminate adjustment of a delay circuit and to reduce its area in a semiconductor device and the noise for high-speed rotation by inserting a second latch means having a clock whose phase is opposite to that of the clock of a third latch means between first and third latch means to obtain a margin of a 1/2 clock with respect to said clock. CONSTITUTION:When an input signal A of plural bits is inputted to a stage 1, the control signal for the input signal A is inputted to a delay array simultaneously. Processings in stages are performed synchronously with clock signals CLK1-CLK4 respectively, and the input A is processed in accordance with these clock signals and is finally outputted. When a latch 2 is inserted, the control signal is outputted by the rise of the clock CLK1 and is inputted to the terminal D of the latch 2. The latch 2 outputs a signal by the rise of the clock CLK1, and it is inputted to a flip flop 3, and the flip flop 3 outputs a signal by the rise of the clock CLK2. Thus, a margin of 1/2 clock is secured with respect to the clock CLK2. |
