发明名称 High-speed binary and decimal arithmetic logic unit
摘要 A combined binary and binary coded decimal (BCD) arithmetic logic unit (binary/BCD ALU) having a binary adder adapted to perform decimal operations on BCD data without impacting the performance of binary operations. The combined binary/BCD ALU has a look-ahead carry binary adder for generating the binary sum or logical combination of inputs to the binary adder to an output (Y), the Y output being arranged in groups of four bits. The binary adder additionally provides carry outputs Coi of the binary additions from each of the groups of four bits of the Y output. A decimal correction unit, responsive to the Y and Coi outputs from the binary adder [ALU means], corrects the binary sum from the binary adder when performing BCD arithmetic. A multiplexer selects the Y output from the binary adder to a result output when performing operations on binary data. Alternately, the multiplexer selects the output from the decimal correction unit to the result output performing operations on BCD data.
申请公布号 US4866656(A) 申请公布日期 1989.09.12
申请号 US19860938670 申请日期 1986.12.05
申请人 AMERICAN TELEPHONE AND TELEGRAPH COMPANY, AT&T BELL LABORATORIES 发明人 HWANG, INSEOK S.
分类号 G06F7/494;G06F7/50;G06F7/508;G06F7/575 主分类号 G06F7/494
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