Memory control system using a single access request for doubleword data transfers from both odd and even memory banks

摘要

A memory access control system has a main memory having a plurality of memory banks divided into two groups, thus enabling parallel processing for data, a command/address bus line, a write data bus line, a read data bus line, and a device for simultaneously activating one request for access to the memory bank belonging to one group and another request for access to the memory bank belonging to the other group.