| 摘要 |
<p>PURPOSE:To attain rationalization such as the areal reduction of an IC chip, by providing a structure having a control circuit connecting the parallel output of a shift register to the data input of a latch circuit in an overlapped state and dividing a latch control signal to select the same. CONSTITUTION:The pixel data for an odd number bit applied to an input terminal 5c is taken in a shift register 8 on the basis of the transmission clock signal inputted to an input terminal 5d. By repeating this operation, predetermined pixel data is prepared in the shift register 8 and an external latch control signal is subsequently applied to an input terminal 5b. Whereupon, a latch control circuit 7 outputs a latch control signal only to a latch circuit 9a for an odd number bit and, therefore, the parallel output signal of the shift register 8 is selectively stored in the latch circuit 9a for the odd number bit and the content of a latch circuit 9b for an even number bit is not altered. In the same way, the parallel output signal of the shift register 8 is selectively stored in the latch circuit 9b for the even number bit and the content of the latch circuit 9a for the odd number bit is not altered.</p> |
