发明名称 TRANSMISSION TIMING CONTROL SYSTEM
摘要 PURPOSE:To attain miniaturization, to reduce cost and to establish synchronization with an opposite side MODEM at a short time by constituting a system in such a way that synchronization by a PLL function is started from the state of phase aberration which is half a conventional example by means of adding a small-scale circuit to a conventional system and changing it. CONSTITUTION:In the MODEM transmitting data based on a transmission timing signal inputted from a data terminal with a transmission data signal, an initialization part 4b outputs a reset signal when the time of T-t/s has passed from a time when a detection part 3a executes sampling at a period (t) and detects the fall of the transmission timing signal ST1 when one bit time length decided by a data transmission speed is set to T. A timing control part 2b attains the function of a PLL circuit with a pulse generation part 1a, compares the phase and synchronizes an output pulse signal ST2 with ST1. A data assembly part 5b samples SD by ST2 so as to extract bits ana assembles them into parallel data in the unit modulating the bits, and outputs it to a main control part 8b. Thus, a phase error comes less than the half of a sampling period and the pulse signal can easily be synchronized.
申请公布号 JPH01226240(A) 申请公布日期 1989.09.08
申请号 JP19880052006 申请日期 1988.03.04
申请人 FUJITSU LTD 发明人 SETO CHIAKI
分类号 H04L7/10;H04L7/033 主分类号 H04L7/10
代理机构 代理人
主权项
地址