发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To earn a delay time with using an inverting circuit and to generate delay in an output by interrupting a prescribed current route when the inverting circuit is operated. CONSTITUTION:When nodal points N11 and N12 are connected and the input potential of an inverting circuit I11 is changed from a low potential to a high potential, the potential of a nodal point N13 in the output side of a delay circuit D11 is in the low potential. Since the gate potential of a transistor Q13 goes to be the high potential, the current route, which flows from a power source in the final step of the delay circuit D11 through the nodal points N12 and N13 to the ground of the inverting circuit I11, is not generated. Accordingly, the potentials of the nodal points N11 and N12 are speedily inverted and the output of an inverting circuit I12 is also inverted from the low potential to the high potential. When the potential of the nodal point in an input side is changed from the low potential to the high potential through the delay time of the delay circuit D11 and discharged by transistors Q12 and Q14, the potential of the nodal point N12 in a switch circuit S11 is inverted from the high potential to the low potential. Accordingly, the output of the inverting circuit I12 is delayed only by the delay time which is obtained by the delay circuit D11.
申请公布号 JPH01225221(A) 申请公布日期 1989.09.08
申请号 JP19880051046 申请日期 1988.03.03
申请人 NEC CORP 发明人 KOMURO TOSHIO
分类号 H01L27/10;H03K5/13 主分类号 H01L27/10
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