| 摘要 |
PURPOSE:To test a peripheral circuit part regardless of a CPU by providing a means which interrupts and separates a data transfer from an internal data processing circuit to the peripheral circuit part, and an interface circuit which transmission-controls a peripheral circuit part testing signal to a bus for the peripheral circuit. CONSTITUTION:In a second test mode, a test mode signal ST2 on a second test mode line L2 is made into an active level by the second level of a mode signal SM impressed to a port P0, the test mode signal ST2 interruption-controls a peripheral bus interface (PRBI) 11 and a buffer B, and the connection between an internal bus (IB) 9 and a peripheral address bus (PRAB) 12 and between the bus 9 and a peripheral data bus (PRDB) 13 is separated. In addition, a circuit TPBI 14 to interface between a port P1 and the PRDB 13 becomes active, and signals Sd impressed to the port P1 are directly inputted to the PRAB 12 and the PRDB 13. Thus, a peripheral circuit part 300 can be tested regardless of a CPU 100. |
