| 摘要 |
An analog-to-digital converter is provided which includes a binary weighted capacitor array (5 through 13) connected with a series of resistors (26) structured as an array. The converter provides for charge correction to compensate for any capacitance deviation in the capacitor array (5 through 13). The converter includes a charge redistribution sequence under the control of a microcomputer (22) to determine the digital value of the analog input using the resistor array (26) to determine the least significant bit positions of the analog input. This same resistor array is also used to correct for the capacitor value deviations in the binary weighted capacitor array (5 through 13). |
