| 摘要 |
PURPOSE:To increase the arithmetic speed of the whole divider by performing a logical operation in accordance with the input value at that time at each point of time by each of a subtracter with control input and a carry foreseeing device without using a clock signal input to proceed with an arithmetic operation step and outputting its result. CONSTITUTION:A subtracter CSI, J with control input prepares a carry generation signal G and a carry propagation signal P expressed by a logical expression Co=G+PCi (Ci is a carry input terminal and Co is a carry output terminal) by using a subtracted bit A and a subtracting bit B. On the other hand, a carry foreseeing device CLA foreseeingly obtains a carry C01 from a subtracter CSI, 1 with control input by the logical operation by using the carry generation signal G and the carry propagation signal P. Since the carry generation signal G and the carry propagation signal P themselves have no connection with a carry propagation from other strings, the final operation result of the carry foreseeing device CLU cans be rapidly obtained. Thus, the arithmetic speed of the whole divider is increased. |
