发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To realize large capacity and high speed by constituting a sense amplifier circuit of a first inversion amplifier and first and second field effect transistors, and constituting a reference voltage generation circuit of third and fourth field effect transistors and a second inversion amplifier. CONSTITUTION:The sense amplifier circuit 100 is constituted of the first field effect transistor QS2 to whose gate the output of the first inversion amplifier is connected and whose source is connected electrically to a digit line, and the second field effect transistor QS1 in which gate potential is controlled so as to always be energized. Also, the reference voltage generation circuit 200 is constituted of the third field effect transistor QD3 controlled so as to always be energized in a readout mode, the second inversion amplifier to input a first node, and a partial circuit connected between a power source and the drain of the fourth field effect transistor QR2. The title device is constituted at least of those devices and a comparison detector. In such a way, since a time balancing a reference voltage at a preset value can be shortened, the large capacity and the high speed can be realized.</p>
申请公布号 JPH01220295(A) 申请公布日期 1989.09.01
申请号 JP19880048313 申请日期 1988.02.29
申请人 NEC CORP 发明人 HASHIMOTO KIYOKAZU
分类号 G11C17/00;G11C7/06;G11C16/06;G11C16/28;H01L21/8247;H01L27/10;H01L29/788;H01L29/792 主分类号 G11C17/00
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