发明名称 SERIAL COMMUNICATION PROCESSOR
摘要 <p>PURPOSE:To simplify the logic of a receiving control part by having a receiving to transit to a second character receiving condition when a mark detection is executed and transit to a break receiving state when a break detection is executed, in the character receiving state of a start-stop synchronization. CONSTITUTION:First, when a starting bit is detected, it is transitted to the state of a character reception 1. In the state of the reception 1, when a mark 1 exists at a receiving character, it is not the break reception, and therefore, it is transitted to the state of a character reception 2. On the other hand, when a stop bit is a space 0, the break detection is obtained and it is transitted to the break receiving state. At this time, since the break reception cannot be obtained in the state of the character reception 2, thus, the logic for the break detection can be simplified.</p>
申请公布号 JPH01218245(A) 申请公布日期 1989.08.31
申请号 JP19880042068 申请日期 1988.02.26
申请人 HITACHI LTD;HITACHI MICRO COMPUT ENG LTD 发明人 OSHIBA MASAFUMI
分类号 H04L29/08;H04L7/04;H04L13/00;H04L29/14 主分类号 H04L29/08
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