| 摘要 |
The circuit arrangement includes a basic circuit for calculating the zeroth approximation and expandable by at least one correction circuit for calculating a first or further approximations. The basic circuit contains a first adder, a second adder, a first constant multiplier, a second constant multiplier, a first absolute-value stage, a second absolute-value stage and a third absolute-value stage which is interposed between a subtracter and the input of the second constant multiplier. The output of the second constant multiplier is coupled to one input of the second adder, whose output provides the zeroth approximation to the value of the complex digital quantity. Each of the two input signals is fed through one of the absolute-value stages to one of the two inputs of the subtracter and the first adder. |
