| 摘要 |
<p>PURPOSE:To reduce the probability of disconnection of a source wiring at an intersecting part with a gate wiring by forming a protecting insulation film and an amorphous silicon layer under the source wiring widely than the width of the source wiring. CONSTITUTION:A gate insulating layer 3, an amorphous silicon layer 4 and a protecting insulation layer 5 are successively stacked on an insulating substrate 1 on which a gate wiring 2 and a gate electrode 7 are formed. Then the layer 5 is selectively removed to form an island-like pattern on the gate electrode 7 and to form the pattern of the layer 5 wider than that of the source wiring under the source wiring over the whole source wiring area. Then an n-type silicon layer 11 and a metallic layer 12 are successively stacked. The metallic layer 12 is patterned like the shape of a source electrode 8 and a drain electrode 9 and the layers 11, 12 are etched by using the patterned parts to form the source electrode 8 and the drain electrode 9. The ITO is evaporated in vacuum and etched to form a source wiring 6 and a picture element electrode 10. Consequently, the level difference of the source wiring 6 can be sharply reduced and the probability of disconnection can be reduced.</p> |
