| 摘要 |
PURPOSE:To calibrate parasitic current generating between an isolation region arranged in an integrated circuit and a semiconductor substrate, by forming a lateral PNP Tr having the same characteristics as a lateral PNP Tr arranged in an integrated circuit in which parasitic current flows, the former being arranged in the vicinity of the latter, and canceling the parasitic current generating in the lateral PNP Tr used in an original circuit by the parasitic current generating in the added PNP transistor. CONSTITUTION:Lateral PNP transistors Q1 and Q2 of a conductivity type having the same characteristics are arranged on a semiconductor substrate. The transistor Q2 is connected with base-open and the emitters of both transistors. Collector terminals of the transistors Q1, Q2 are connected with the collector terminals of inverse conductivity type lateral NPN transistors Q3, Q4 which are arranged corresponding with Q1, Q2. The collector terminal of the lateral PNP transistor Q2 of a conductivity type is connected with the bases of the lateral NPN transistors Q3, Q4. The collector terminal of the lateral PNP transistor Q1 of a conductivity type is made an output terminal. As a result, when parasitic current IP flows in the PNP transistor Q1, the similar current flows in Q2. |
