| 摘要 |
<p>1,267,979. Television. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 17 Oct., 1969 [21 Oct., 1968], No. 51113/69. Heading H4F. A sync. separator comprises an amplitude limiter to which the video signal is applied and the output of which is coupled to the base of a transistor forming a clipping stage, the output of the separator being taken from the collector of the transistor, and the emitter of the transistor being D.C. coupled to an R.C. network, having a short time constant relative to the period of the field sync. pulses, and to a biasing electrode in the amplitude limiter. As shown, Fig. 1, the video signal 4 is applied to the emitter of transistor 1 constituting the amplitude limiter, the collector of which is corrected to a clipping stage 2 comprising transistors 7 and 8 connected as a Darlington pair. Line sync. pulses appear at the collector of transistor 8, the emitter of which is coupled to an R.C. network 10 which supplies the biasing voltage to the base of transistor 1 to control the limiting level. The field sync. pulses are separated from the limited video signal by means of a differential amplifier 3 and an R.C. integrating circuit 19. The resulting waveform 23<SP>1</SP> may be applied to a clipping stage (not shown). Bipolar transistors 1 and 14 may be replaced by MOSTs to reduce the loading on network 10.</p> |
