发明名称 |
Digital circuit for suppressing fast signal variations |
摘要 |
A digital circuit which receives a serial input signal and which suppresses fast signal variations. The digital circuit includes an integrator circuit (1) which generates a multi-bit signal by integration of the serial input signal. The output signal of the integrator circuit is applied to an evaluation circuit (2) which generates a serial output signal which assumes a first state when the multi-bit signal exceeds a first threshold value and a second state when the multi-bit signal is below a second threshold value.
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申请公布号 |
US4862404(A) |
申请公布日期 |
1989.08.29 |
申请号 |
US19870071695 |
申请日期 |
1987.07.09 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
SCHWARTZ, WOLFGANG;WARMUTH, OTTO L.;GRZYB, CLAUS D. |
分类号 |
H03K5/1252;G06F7/66;H03H17/02;H04B10/06;H04L25/03;H04L25/08;H04Q9/00 |
主分类号 |
H03K5/1252 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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