| 摘要 |
PURPOSE:To improve the degree of integration by forming one electrode for a capacitance element in one of two mutually adjacent memory cells by a first conductive layer coated with a patterning resistant film shaped by deposition and forming one electrode for a capacitance element in the other of the two memory cells by patterning a second conductive layer. CONSTITUTION:A conductive layer 41 as a polycrystalline Si layer, etc., is shaped onto an inter-layer insulating film 18 and into openings 21a, 22, and a patterning-resistant film 42 is formed onto the conductive layer 41. The patterning-resistant film 42 is patterned, and the conductive layer 41 is patterned, using the patterning-re sistant film 42 under the state as a mask, thus shaping an electrode 23a. An opening 21b is formed, and a conductive layer as a third layer polycrystalline Si layer, etc., is shaped onto the whole surface on a semiconductor substrate 11 under the state. An electrode 23b is formed by patterning the conductive layer. The patterning-resistant film 42 on the electrode 23a is removed, and dielectric layers 25a, 25b and an electrode 26, etc.,are shaped. Accordingly, one electrode for a capacitance element is formed extending over approximately the whole region of a memory cell, thus acquiring the high degree of integration. |
