| 摘要 |
PURPOSE:To improve the degree of integration by forming a first conductive layer and a second conductive layer onto a semiconductor region in which a memory cell is formed, the two layers being divided into upper and lower layers so as to have mutually superposed sections and shaping capacitance by interposing a dielectric film between the first conductive layer and the second conductive layer. CONSTITUTION:A conductive layer 12 and a conductive layer 14 are formed divided into upper and lower two layers so as to have mutually superposed sections on a semiconductor region, in which a memory cell 20 is shaped, while a dielectric film 13 is interposed between the layers 12 and 14. The conductive layers 12, 14 are used respectively as wirings forming the circuit connection of the memory cell 20, the conductive layer 12 shapes the wiring connected to an N conductivity type diffusion layer 7 for extracting a cathode side electrode for a Schottky-barrier-diode DS, and the conductive layer 14 is connected to a word line W1 through a wiring 18 and the anode side of the Schottky- barrier diode DS. Accordingly, required capacitance can be acquired without increasing the area of the layout of the memory cell, thus improving the degree of integration. |
