| 摘要 |
PURPOSE:To always inhibit a stable phase control by employing the counted value output of a counter in which a counted value is increased or decreased as a phase control signal by a phase lead pulse signal or a phase lag pulse signal responsive to a phase error signal. CONSTITUTION:A phase comparator 11 compares a phase control reference clock phiL with the phase signal FPS of a motor 7 in phase to output a signal PE. A phase error discriminator 12 outputs a lead phase error signal P1 or a lag phase error signal P2 in response to the signal PE. A lead pulse generator 13 and a lag pulse generator 14 respectively output clock pulse signals P1OT, P2OT having N times of frequency as large as the clock phiL during the pulse widths of the signals P1, P2. An incremental/decremental counter 15 down-counts the signal P1OT, and up-counts the signal P2OT, and outputs a counted value as a phase error correction signal. |
