发明名称 RECOGNITION OF FAILURE OF MULTI-LAYER PRINTED-CIRCUIT BOARD
摘要 PURPOSE:To enable a mark at an improper part accompanied by heat at the time of lamination to be colored, to enable improper areas to be detected easily from the outer layer, and to eliminate the need for inspection of improper areas by laminating after providing identification mark at an improper area of inner-layer pattern which develops color due to heat. CONSTITUTION:After forming an inner-layer pattern within a multiple chamfering inner substrate 11, an improper area is detected by inspection and paint is applied to the entire unit substrate with improper areas to form a mark 12. Then, a glass epoxy prepreg 13 and a copper foil 14 are superposed on both surfaces of the substrate 11, heat is applied to, and they are laminated. Then, after drilling a reference hole on the substrate 11, a multiple chamfering outer layer pattern is formed. As a result, paint applied to an improper area of inner-layer substrate develops color due to application of heat on lamination and can be visually recognized clearly from the area of outer-layer pattern where copper foil of outer-layer pattern is eliminated.
申请公布号 JPH01214198(A) 申请公布日期 1989.08.28
申请号 JP19880040455 申请日期 1988.02.23
申请人 TOSHIBA CORP 发明人 OSANAI HISASHI
分类号 H05K1/02;H05K3/46 主分类号 H05K1/02
代理机构 代理人
主权项
地址