| 摘要 |
PURPOSE:To increase the quantity of delay with a few number of stages easily by inserting a P-channel MOS transistor(TR) and an Nchannel MOS TR, increasing an output impedance so as to increase the time required to charge/discharge the load capacitance. CONSTITUTION:Sources and gates of P-channel MOS TRs of inverter gates 101-110 are all connected and connected to a drain of a P-channel MOS TR 111 connecting to the 2nd power supply and the source of the P-channel MOS TR 111 is connected to a 1st power supply. On the other hand, sources and gates of N-channel MOS TRs of the inverter gates 101-110 are all connected and connected to a drain of an N-channel MOS TR 112 connecting to the 1st power supply. Furthermore, the source of the N-channel MOS TR 112 is connected to a 2nd power supply, the input terminal 1 is connected to the input of the inverter gate 101 and the output terminal 2 is connected to the output of the inverter gate 110. Thus, the quantity of delay is increased with a few number of stages. |
