发明名称 TRANSMISSION AND RECEPTION SYSTEM
摘要 PURPOSE:To reduce the insertion loss at the transmission of data signals, to eliminate clock signals and to attain high-speed transmission, by inhibiting the retransmission of reproduced data given from a bidirectional bus when reception reproducing data is detected and an inhibit signal is detected. CONSTITUTION:The first stage circuits B11, D12 and the final stage circuits A12, C11 are connected between a bidirectional bus transmission line L1 and unidirectional bus transmission lines L11, L12 of a data transmission system, and an inhibit pulse generating circuit 1 is connected between circuits D12 and A12. A delay circuit 2, an AND circuit and an OR circuit are connected between the circuits B11 and the circuit C11, and a collision preventing circuit 3 and the OR circuit are connected between the circuits A12, B11 and the circuit C11. A reproduced data signal from the transmission line L12 is detected at a circuit 1 and when the inhibit signal is detected, the retransmission of the reproduced given from the transmission line L1 is inhibited, the clock signal is not required, and the insertion loss at the transmission of the data signal is reduced with simple constitution.
申请公布号 JPS58184846(A) 申请公布日期 1983.10.28
申请号 JP19820066886 申请日期 1982.04.21
申请人 FUJITSU KK 发明人 SAITOU SEIICHI
分类号 H04L5/14;H04L12/40 主分类号 H04L5/14
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