发明名称 DELAY CIRCUIT
摘要 PURPOSE:To stably generate the delay of fixed period signal transmission by not concerning with pull-down and pull-up actions in the early stage continuity of two switch devices with a capacity load and concerning after a fixed period when the continuity early stage passed. CONSTITUTION:Just after an input signal is changed into an 'L', a P channel FET42 is continued, a current I1 flows, a current I2 flows through resistance Rs, and as a result, since the source.drain current of a P channel FET43 does not flow, a current Lu to a C1 does not flow. Consequently, the level of an output side is an 'L' in the period while it rises at the charging electric potential fixed value of a capacity CB, and the delay action of an inter-input/output- signal is executed for that time. On the other hand, just after the input signal is changed into an 'H', an N channel FET47 is continued, a current I4 flows, a current Is flows through the resistance Rs, and as a result, since the source.drain current does not flow, the current from the capacity load C1 does not flow. Consequently, the output side level maintains the 'H' in the period while the charging electric potential is the fixed value, and the delay action of the between input/output signals is executed.
申请公布号 JPH01213023(A) 申请公布日期 1989.08.25
申请号 JP19880038809 申请日期 1988.02.22
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 SEKI TERUO;IWASE AKIHIRO;NAGAI SHINJI
分类号 H03K5/00;H03K5/13 主分类号 H03K5/00
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