DATENVERARBEITUNGSSYSTEM MIT CACHE-SPEICHER

摘要

An improved memory architecture includes a processor (CPU) 30 coupled over a bus 33 to a plurality of dynamic random access memory (DRAM) banks 32, 34. A cache memory 36, 38 is coupled between each of the DRAM banks and the bus. Each cache includes a static memory for data which is a subset of the data in its respective DRAM. An address provided by the CPU is composed of a base address and tag address. A bus interface controller (BC) within each cache compares the base address and ignores it if it falls outside the range of addresses stored within its DRAM. If it fails within the range, and the processor is executing a READ operation, the tag address is compared to a plurality of tags representing data in the cache. If a match occurs, then cache control logic initiates a READ cycle to the cache and provides the data to the CPU. In the event no match is found, the logic initiates a DRAM access cycle. A tag address within the cache is then randomly chosen and the data read from the DRAM is provided to the processor and stored in the cache at the location of the randomly chosen tag. The previous data corresponding to the randomly chosen tag is stored in the DRAM if a modify bit indicates that it represents updated data not previously stored in the DRAM. Similar operations are provided in the case of a WRITE processor command, whereby data to be written is stored in the cache and a randomly chosen tag address is deleted and the DRAM updated if required. <IMAGE>