| 摘要 |
PURPOSE:To shorten the time needed for operations by obtaining the shift number necessary for normalization for addition/subtraction of a floating point mantissa part from the higher two bits of a mantissa and the exponent difference obtained through the digit matching of the mantissa or from all other bits except the most significant bit. CONSTITUTION:A normalization control circuit 106 consists of a combination circuit supplies the outputs Ez and SM2 of an exponent computing element 102, the bits 2' and 2'' of the output of a mantissa computing element 104, and an addition/subtraction instruction signal 108 received from outside and mentioned later and outputs a normalized number of shifts designating signal and a selection signal SEL. With application of the circuit 106, the bit number needed for normalization of the output of the element 104 is calculated by a decoder 105 or based on the five bits including the higher two bits of the output of the element 104. Then the output of the decoder 105 is used only when the circuit 106 is unable to logically decide the bit number necessary for normalization. As a result, the overall time necessary for obtaining the number of shifts for normalization can be shortened on an average in case the addition/subtraction are carried out for the large number of floating points. |
