| 摘要 |
PURPOSE:To reduce the electric current at the time of waiting states and, at the same time, to realize highly reliable refreshing operations by changing the potential of a bit line when the electric charge of a memory cell is read out to another bit line paired to the first mentioned bit line. CONSTITUTION:When writing is made in a memory cell 1a, a transistor Q1 is turned on and the potential Vcc of a bit line BL is impressed on a capacitor C1. After the transistor Q1 is turned off the bit line BL and its paired bit line -BL are equalized to the potential of Vcc/2 by means of a bit line equalizing signals phiEQ and the potential is maintained. On the other hand, capacitors C3 and C4 of dummy cells 4a and 4b are conducted to an earthing line GL and their potential becomes 0V. When a refreshing mode is set, the capacitor C1 is conducted to the bit line BL and the potential of the bit line BL rises. Moreover, the capacitor C4 is conducted with the bit line -BL and the potential of the bit line -BL drops. Therefore, influences of the potential change accompanied by the elapse of time of the memory cells 1a and 1b can be reduced and, as a result, the storage reliability is increased and the refreshing flow interval can be extended. |
