Cache memory reset responsive to change in main memory

摘要

A circuit for resetting a multi-bit word in a digital memory at a selected address receives a word reset signal to cause entry into the selected address of a multi-bit word wherein all the bits are set to the same level and a parity bit is set to a value corresponding to parity in the multi-bit word. The circuit includes a parity generator which receives a multi-bit input data word and generates at least one parity bit therefrom. During a normal write operation, the multi-bit input data word and the parity bit are written into the digital memory at the selected address. During a word reset signal, output from the parity generator and the multi-bit input data word are blocked from entry into the memory.