| 摘要 |
PURPOSE:To obtain a high performance receiver with less reception frequency deviation by adopting the constitution of a PLL circuit such that a reference oscillator signal having nearly equal oscillation frequency to a reception normal intermediate frequency is used as a synchronization detection carrier and the phase error voltage between the received intermediate frequency signal and the reference oscillator signal is fed back to a local VCO. CONSTITUTION:The PLL circuit consists of a VCO 21 as a local oscillation signal source, the reference oscillator 22 having a frequency nearly equal to the received nominal intermediate frequency, a multiplier 8 between an in-phase component and an orthogonal component of an orthogonal synchronizing detection circuit A, a timing clock recovery circuit 9, a phase comparator 10 and LPF 11. In the case of the reception of a received wave, the wave is mixed terms with frequency with an output signal of a VCO 21 by a mixer 2 to produce a reception intermediate frequency signal. The reception intermediate frequency signal is subjected to synchronization detected by using the reference signal from the reference oscillator 22 as a recovery carrier. Then the phase of the recovered clock and the phase being the result of multiplication between the in-phase component and the orthogonal component being an output signal of orthogonal synchronization detection are compared and its phase error information is fed back to the VCO 21, which is controlled so that the reference oscillator signal and the recovered carrier are equal to each other, thereby establishing synchonization detection. |
