| 摘要 |
A frequency synthesizer system generates a clock signal having an adjustable, accurate and stable frequency. The synthesizer produces a first reference frequency FR and an adjustable first intermediate frequency F1 equal to the frequency FR divided by a selectable number (N2/N1) which permits course adjustment of the frequency in steps over a prescribed range. The frequencies FR and F1 are then mixed and filtered to produce a second intermediate frequency FR+F1. The system also generates a second reference frequency F3 which is finely adjustable over a range in the order of magnitude of the frequency difference between two successive steps of the first intermediate frequency F1. This second reference frequency is mixed with the second intermediate frequency and the result is filtered to produce a final frequency FR+F1+F3.
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