| 摘要 |
PURPOSE:To simplify algorithm and a circuit by performing the parallel development of a frame pattern in a digital string, and detecting an error by a NAND circuit after combining (m) bits of the frame pattern by every (n) bits. CONSTITUTION:Input digital data A is developed to the frame pattern of (m) bits at a parallel developing circuit 1, and is checked at a decision circuit 2, and when the errors of (n) or more bits exist, the error C is outputted. Here, the decision circuit 2 is constituted of inverters (2-1-2-3), 2-input NAND circuits (2-4-2-9), and a 6-input NAND circuit 2-10. A developed frame pattern is set as the pattern of 4 bits, and when the errors exist in two or more bits, the errors of 2 bits are detected at three inverters (2-1-2-3) and the 6-input NANDs (2-4-2-9). Also, the errors exceeding two are detected by the 6-input NAND 2-10. |
