发明名称 PLATED WIRE MEMORY
摘要 A plated wire core memory array is described in which the core wires are divided into two sets which are placed on either side of word conductors. The flux emanating from one core during excitation passes through another core on the other side of the word conductors so that fluctuations in the switching fields due to changes in the pattern of stored information, are reduced or suppressed.
申请公布号 US3654627(A) 申请公布日期 1972.04.04
申请号 USD3654627 申请日期 1970.06.30
申请人 RICHARD L. SNYDER 发明人 RICHARD L. SNYDER
分类号 G11C11/04;(IPC1-7):G11C11/14 主分类号 G11C11/04
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