发明名称 |
High speed zero power reset circuit for CMOS memory cells |
摘要 |
A reset circuit for a CMOS memory array is disclosed wherein the voltage supply for the standard six transistor memory cell is replaced by a pair of parallel connected transistors disposed between a fixed voltage source and the memory cell. The transistors are controlled by the reset signal and are complementary in that one is n-channel and the other is p-channel. The n-channel transistor is sized to prevent excess current flow to the memory cells to prevent an excessive charge build up therein for a logical "1" representation. In addition, the n-channel transistor provides a Vtn drop thereacross to prevent current flow in the memory cells during reset.
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申请公布号 |
US4858182(A) |
申请公布日期 |
1989.08.15 |
申请号 |
US19860944643 |
申请日期 |
1986.12.19 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
PANG, ROLAND H.;CHIU, EDISON H. |
分类号 |
G11C7/20 |
主分类号 |
G11C7/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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