| 摘要 |
A computer system has a central processing unit and a video display processor both of which must directly access the system memory. The display processor must access the memory once in a given time period which time period is long enough that several accesses by the central processing unit and the display processor would be possible. The system includes a memory controller which allows the central processing unit to have memory access priority over the display processor, as long as sufficient time remains in the period for the display processor to complete its access after the access by the processing unit. If insufficient time remains, the display processor has priority for memory access. To implement this priority scheme, a new system memory organization is employed, dividing the memory into banks or bit planes and providing each bank with a respective temporary storage latch that loads to a respective shift register. The serial data stream from the shift registers supply the video display processor video code information on a continuing basis. The timing of memory read out to the temporary storage latches is timed in accordance with the memory priority protocol.
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