| 摘要 |
PURPOSE:To decrease the number of counters and to simplify the constitution of a gate circuit, by allowing a counter that delivers successively sampling signals to a key common signl line to servo also as a chattering avoiding counter when no key is operated. CONSTITUTION:When any one of key input signal lines KI1-KI4 is operated, an FF4 is via an OR circuit 1. Then an interruption signal INT is transmitted to a CPU via a one-shot circuit 11. Gate opening signals KIP and KCR are supplied from the CPU to open successively gate circuits 2a-2d and 10a-19c. Then key input data KI and key common data KO are written successively. When the key operation is released, the signal 0 is supplied to an FF4, an inverter 3 and a one-shot circuit 5 respectively to reset a counter 7. At the same time, the counter 7 counts the clocks CK which are supplied via an AND gate 6. When the count value of the counter 7 reaches the maximum level and the sufficient time elapses to avoid the chattering which is produced when the key operation is released, the signal 1 is delivered from an AND gate 9 to reset the FF4. Thus the signal INT is cut off. |
