SWITCHED IMPEDANCE EMITTER COUPLED LOGIC GATE

摘要

There is disclosed herein an ECL gate using switchable load impedance means to allow the gate to be placed in a low power-consumption mode while preserving the logic state existing at the outputs of the gate at the time it is switched into the low-power mode. N-channel or Pchannel MOS transistors are used as the switchable load impedances. The gates of these transistors are coupled to a MODE control signal which causes the MOS transistors to switch between high-impedance and low-impedance states. Another MOS transistor having its gate coupled to the same MODE control signal is used as the current source for the bias current to the conventional ECL current mirror. When low-power mode operation is desired, all the MOS transistors are switched to their high-impedance states. This reduces the bias current flowing through the ECL gate, thereby reducing its power consumption. The logic states at the output nodes are preserved by virtue of the load impedance of the ECL switching transistors having increased simultaneously with their collector currents having decreased.