| 摘要 |
<p>A serial access memory device with the improved cascade buffer circuit (20') for controlling serial access operation which has a small number of external terminals (Cin, Cout, FL) is disclosed. The cascade buffer circuit (20') includes first and second external terminals (Cin, Cout), a first control circuit for enabling the memory device to perform write operation and read operation when the level at the first external terminal (Cin) rises or falls and when the level at the first external terminal (Cin) falls or rises, respectively and a second control circuit for operatively causing the second external terminal (Cout) rise or fall when the memory device completes write operation and causing the second external terminal (Cout) fall or rise when the memory device completes read operation, respectively.</p> |
