| 摘要 |
The memory cell of the present invention is a three transistor cell, including two floating gate MOS transistors connected in series with a select transistor. The source of the first memory cell floating gate memory transistor is connected to a source of a first potential. Its gate is connected to a first sense line. Its drain is connected to the source of the second memory cell floating gate transistor. The gate of the second memory cell floating gate transistor is connected to a second sense line. The drain of the second memory cell floating gate transistor is connected to the source of a select transistor. The gate of the select transistor is connected to a word line. The source of the select transistor is connected to a bit line. A plurality of memory cells may be connected together as a byte, and may be placed in an array. The gates of the select transistors are connected together. A word line signal which drives the gates of the select transistors also drives the gates of two sense line byte select transistors which enable the sense line signals to appear on only the gates of the memory cell floating gate transistors of the selected byte.
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