| 摘要 |
PURPOSE:To attain high data transmission speed easily by applying serial/ parallel conversion to a data string into n-string, extending the clock period by n-time and detecting the synchronization. CONSTITUTION:The length of a frame of string conversion means 1, 3 is selected to be an integral number of multiple of (n) ((n) is an integral number being two or over) bits, a 1st data string including consecutive n-bit frame synonymizing bit is subject to serial/parallel conversion into n-string and the result is outputted as the data strings of 2nd-(n+1)th data strings in the corder from the string with the most advanced phase to the lagged phase. The delay means 4, 5 retard the i-th ((i) is an integral number of 2-n) data string by one bit, and pattern detection means 6-8 output a detection signal when the parallel bit pattern of the 2nd-(n+1)-th data strings is coincident with the predetermined bit pattern. Then a frame pulse generating section 10 outputs a frame pulse in the timing of the detection signal outputted repetitively in the period of the frame among the 1st-nth detection signals. Thus, the data transmission speed is increased by using low speed logic circuit components. |
