| 摘要 |
A method for testing layering processes of integrated circuit construction for random defects. A test structure is employed having a plurality of micro-patterns covering a wafer, the patterns being fabricated in accord with a unit process of an integrated circuit manufacturing operation. The patterns are fabricated either with a lower conductive level covered by an insulative layer and an upper conductive level, all having pads which may be probed at the upper level, or a single conductive layer. By repeating tests in various unit processes, random defects can be isolated to individual unit processes. Nine patterns are disclosed which form a universal test set.
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