发明名称 TESTING CIRCUIT FOR LARGE SCALE INTEGRATED CIRCUIT
摘要 PURPOSE:To improve the trouble detecting rate of a whole circuit by separating an internal bus output signal and a pseudo-internal bus signal according to a selecting signal. CONSTITUTION:A second selector circuit 11 is provided to select whether the internal bus output signal is set in a scan pass system flip-flop circuit 1, the pseudo-internal bus output signal is held or a scan pass signal by shift operation is set according to a shift operation control signal and the selecting signal. A third selector circuit 31 is provided to select whether the selecting signal is held in a scan pass system flip-flop circuit 3 for test control or the scan pass signal by the shift operation is set according to the shift operation control signal. Then, a first selector circuit 2 separates the internal bus output signal and pseudo-internal bus output signal by the selecting signal. Accordingly, the observation of the internal bus output signal can be easily executed and a limit to be given to bus activation in the circuit can be canceled. Thus, the trouble detecting rate of the whole circuit can be improved.
申请公布号 JPH01196634(A) 申请公布日期 1989.08.08
申请号 JP19880019566 申请日期 1988.02.01
申请人 NEC CORP 发明人 TAKAHATA SUNAO
分类号 G06F11/22;G01R31/28 主分类号 G06F11/22
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