| 摘要 |
PURPOSE:To prepare a bit mask at high speed even when the number of the bits of input data is large by providing respectively a part mask preparing circuit to prepare part mask data corresponding to respective divided blocks and a parity correcting circuit to prepare a parity. CONSTITUTION:Part mask preparing circuits (11-1)-(11-l) to divide input data to plural blocks and prepare the part mask data corresponding to respective divided blocks and parity correcting circuits (12-1)-(12-l) to prepare the parity are respectively provided. Thus, compared with the conventional circuit to prepare a bit mask by passing all input data through an exclusive OR circuit, the number of the times in which the input data passes through the exclusive OR circuit is minimized and the bit mask can be prepared at high speed. Further, by providing plural OR circuits and plural AND circuits at respective parity correcting circuits (12-1)-(12-l), a bit mask in accordance with the different rule can be also obtained. |
