发明名称 COMMUNICATION SYSTEM
摘要 <p>PURPOSE:To lower the slip probability of data in a buffer by inverting the deviating direction of the frequency of a self-feeding clock outputted at every hit of a signal being supplied from a wide area communication network. CONSTITUTION:When the hit is generated in a clock signal in a wide area network, a clock hit detection circuit 39 in a network synchronizing device 49 detects the fact, and the output signal of an inversion circuit 101 is inverted. Thus, the output signal of the inversion circuit 101 is inverted at every hit of the clock signal, and the deviating direction of a clock outputted from a VCO103 is inverted corresponding to the above inversion. Thereby, the input signal of the VCO103 is inverted at every hit of the clock extracted from the signal of the wide network area, and the deviating direction of the frequency of the clock signal in a loop type communication system is inverted. In such a way, the direction of the change of the phase difference of read/write in a third buffer in a central office interface 45 is also inverted, thereby, the slippage frequency of data can be reduced.</p>
申请公布号 JPH01195736(A) 申请公布日期 1989.08.07
申请号 JP19880020644 申请日期 1988.01.30
申请人 NIPPON TELEGR & TELEPH CORP <NTT>;TOSHIBA CORP 发明人 MORI SHINICHI;YAMAGISHI OSAMU
分类号 H04L7/00 主分类号 H04L7/00
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