| 摘要 |
PURPOSE:To eliminate digit shift processing and to miniaturize the scale of a multiplier by executing an upper filling processing in which (BPLX2+1) in a formula is made (BITS+1) by means of an upper filling processing circuit in case of operating a specific formula. CONSTITUTION:For operating a formula I, the following are provided: a means 21 to upper filling of (BPLX2+1) in the formula I to (maximum allocated bit number+1)-pieces of bits, a multiplier means 22 to multiply an output from the means 21 by that from a dynamic range DR, and a means 23 which takes the high-order (the bit number of a difference data DELTADATA+1)-pieces of bits from a result of the multiplication in the means 22 and which applies rounding to the least significant bit and thus decodes the difference data DELTADATA. As a result, in case a decoder dedicated to no-edge-matching, a digit shift in the formula I also can be obtained simultaneously by the circuit 21, therefore, the multiplier 22 can be miniaturized. |
