发明名称 |
Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors |
摘要 |
Control logic for controlling references to a cache (24) including a cache directory (62) which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory (62) for cache data-array addresses. A cache-configuration register and control logic (64) splits the cache directory (62) into two logical directories, one directory for controlling requests from a first processor and the other directory for controlling requests from a second processor. A prefetch buffer (63) is provided along with a prefetch control register for splitting the prefetch buffer into two logical channels, a first channel for handling prefetches associated with requests from the first processor, and a second channel for handling prefetches associated with requests from the second processor.
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申请公布号 |
US4853846(A) |
申请公布日期 |
1989.08.01 |
申请号 |
US19860890859 |
申请日期 |
1986.07.29 |
申请人 |
INTEL CORPORATION |
发明人 |
JOHNSON, DAVID B.;EBERSOLE, RONALD J.;HUANG, JOEL C.;NEUGEBAUER, MANFRED;PAGE, STEVEN R.;SELF, KEITH S. |
分类号 |
G06F13/36;G06F9/38;G06F12/08 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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地址 |
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