| 摘要 |
PURPOSE:To provide a period resolution in excess of that obtained by a conventional digital circuit by extending the period generated from a counter giving the period when the output of an accumulator exceeds the resolution of the counter. CONSTITUTION:A counter 12 is decremented by T12 times and when the content is '0', a pseudo period pulse is generated and the next clock initializes the counters 12, 16 again and updates a resistor 15. In this case, since the output of an adder 14 in the sum of outputs T11, T12 of the register 13 and a value T12 in the register 15, when the value T12 is 0.5 or over, an integral value T13 outputted from the adder 14 is the addition of '1' to the value T11 and the length of the pseudo period is expanded. Moreover, the output of the adder 19 is the sum of outputs T15, T16 of the register 18 and a value T12 of the register 15 and when the sum of T16, T12 is over '1', the integral value T17 of the output of the adder 19 is the addition of '1' to the value T15 and the delay time is extended. Thus, the period of delicate resolution is obtained. |
