| 摘要 |
In an arithmetic unit comprising a partial product circuit for calculating a plurality of partial products for two numbers and a Wallace tree responsive to the partial products for producing a plurality of tree outputs which gives a total product of the two numbers when summed up, an addend is supplied to the Wallace tree as an additional partial product. The arithmetic unit produces a resultant sum of the total product plus the addend. The addend may be supplied to the Wallace tree from one or more registers therefor. Alternatively, a result register is used for the total product with the total product supplied to the Wallace tree as the addend. As a further alternative, an additional register is used for a third number which is used with bit shifts as the addend. In this last event, the arithmetic unit preferably produces a sum selected from the resultant sum.
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