发明名称 Dual path switch gate array
摘要 A dual path switch (DPS) circuit for interfacing between arithmetic elements of a computer for performing Fast Fourier Transforms. The ratio of power consumption to signal resolution is very low. The DPS has very high frequency resolution, and to conserve power, many of its registers are reset to a logic low status when they are not in use. The DPS includes a diagnostic system which, upon a hardware failure, identifies the faulty gate and specifies the nature of the fault. The diagnostic system also provides a fault signal for use in testing for the mean time between failures.
申请公布号 US4852094(A) 申请公布日期 1989.07.25
申请号 US19870119363 申请日期 1987.11.10
申请人 EATON CORPORATION 发明人 WANG, CHUNG-TAO D.
分类号 G01R31/3185;G06F11/00;G06F11/34;G06F17/14 主分类号 G01R31/3185
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